-- Description    : Calcul du code RS(204,188,8)
-- Littérature : 
--   Lin and Costello, Error Control Coding.
 
--   Morelos-Zaragoza, The art of error correcting coding.
 
-- Reed-Solomon RS(204,188,T=8) réduit.
 
-- issue du code original RS(255,239,T=8).
 
-- Polynome primitif : p(x) = x^8 + x^4 + x^3 + x^2 + 1. 
 
-- Polynome générateur : G(x)=(x-a^0)(x-a^1)...(x-a^15) over a Galois field of GF(256).
 
-- All registers are driven by common clock (clk), clock enable (ce), and asynchronous reset (xgsr) signals. This
 
-- provides ultimate flexibility in integration of the core into larger systems. The registers are clocked on the rising
 
-- edge of 'clk', enabled by a high on 'ce', and asynchronously reset by a high on 'xgsr'. The 'ce_fec' signal controls 
 
-- whether the core is calculating the parity (high) or shifting out the calculated parity (low). 
 
-- f_rscalcul Blocks perform modulo 2 addition of the input symbols.
 
-- f_rscalcul Blocks perform a finite field multiplication, over the Galois field, of a constant and the input symbol.
 
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
use work.pkg_util.all;
entity rs_encoder is
    port(
        xgsr           : in  std_logic;                     -- reset global asynchrone
 
         clk            : in  std_logic;                     -- horloge de traitement
 
         din            : in  std_logic_vector(7 downto 0);  -- Bus de donnée d'entrée
 
         ce             : in  std_logic;                     -- A '1' lorsque les données d'entrées sont valides 
 
         start          : in  std_logic;                     -- A '1' lors de la présence du premier octet entrant en compte dans le calcul du BIP8
 
         ce_fec         : in  std_logic;                     -- A '1' lors du calcul du fec sur des octets d'entrée valident
 
         dout           : out std_logic_vector(7 downto 0)); -- données incluant le code correscteur d'erreur
 
end rs_encoder;
architecture A of rs_encoder is
 
  function f_gfmult(a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0))
    return std_logic_vector is
    variable result : std_logic_vector(7 downto 0);
  begin
    result(0) := (b(0) and a(0)) xor (b(1) and a(7)) xor (b(2) and a(6)) xor (b(3) and a(5)) xor (b(4) and a(4)) xor 
                 (b(5) and a(3)) xor (b(5) and a(7)) xor (b(6) and a(2)) xor (b(6) and a(6)) xor (b(6) and a(7)) xor 
                 (b(7) and a(1)) xor (b(7) and a(5)) xor (b(7) and a(6)) xor (b(7) and a(7));
    result(1) := (b(0) and a(1)) xor (b(1) and a(0)) xor (b(2) and a(7)) xor (b(3) and a(6)) xor (b(4) and a(5)) xor 
                 (b(5) and a(4)) xor (b(6) and a(3)) xor (b(6) and a(7)) xor (b(7) and a(2)) xor (b(7) and a(6)) xor 
                 (b(7) and a(7));
    result(2) := (b(0) and a(2)) xor (b(1) and a(1)) xor (b(1) and a(7)) xor (b(2) and a(0)) xor (b(2) and a(6)) xor 
                 (b(3) and a(5)) xor (b(3) and a(7)) xor (b(4) and a(4)) xor (b(4) and a(6)) xor (b(5) and a(3)) xor 
                 (b(5) and a(5)) xor (b(5) and a(7)) xor (b(6) and a(2)) xor (b(6) and a(4)) xor (b(6) and a(6)) xor 
                 (b(6) and a(7)) xor (b(7) and a(1)) xor (b(7) and a(3)) xor (b(7) and a(5)) xor (b(7) and a(6));
    result(3) := (b(0) and a(3)) xor (b(1) and a(2)) xor (b(1) and a(7)) xor (b(2) and a(1)) xor (b(2) and a(6)) xor 
                 (b(2) and a(7)) xor (b(3) and a(0)) xor (b(3) and a(5)) xor (b(3) and a(6)) xor (b(4) and a(4)) xor 
                 (b(4) and a(5)) xor (b(4) and a(7)) xor (b(5) and a(3)) xor (b(5) and a(4)) xor (b(5) and a(6)) xor 
                 (b(5) and a(7)) xor (b(6) and a(2)) xor (b(6) and a(3)) xor (b(6) and a(5)) xor (b(6) and a(6)) xor 
                 (b(7) and a(1)) xor (b(7) and a(2)) xor (b(7) and a(4)) xor (b(7) and a(5));
    result(4) := (b(0) and a(4)) xor (b(1) and a(3)) xor (b(1) and a(7)) xor (b(2) and a(2)) xor (b(2) and a(6)) xor 
                 (b(2) and a(7)) xor (b(3) and a(1)) xor (b(3) and a(5)) xor (b(3) and a(6)) xor (b(3) and a(7)) xor 
                 (b(4) and a(0)) xor (b(4) and a(4)) xor (b(4) and a(5)) xor (b(4) and a(6)) xor (b(5) and a(3)) xor 
                 (b(5) and a(4)) xor (b(5) and a(5)) xor (b(6) and a(2)) xor (b(6) and a(3)) xor (b(6) and a(4)) xor 
                 (b(7) and a(1)) xor (b(7) and a(2)) xor (b(7) and a(3)) xor (b(7) and a(7));
    result(5) := (b(0) and a(5)) xor (b(1) and a(4)) xor (b(2) and a(3)) xor (b(2) and a(7)) xor (b(3) and a(2)) xor 
                 (b(3) and a(6)) xor (b(3) and a(7)) xor (b(4) and a(1)) xor (b(4) and a(5)) xor (b(4) and a(6)) xor 
                 (b(4) and a(7)) xor (b(5) and a(0)) xor (b(5) and a(4)) xor (b(5) and a(5)) xor (b(5) and a(6)) xor 
                 (b(6) and a(3)) xor (b(6) and a(4)) xor (b(6) and a(5)) xor (b(7) and a(2)) xor (b(7) and a(3)) xor 
                 (b(7) and a(4));
    result(6) := (b(0) and a(6)) xor (b(1) and a(5)) xor (b(2) and a(4)) xor (b(3) and a(3)) xor (b(3) and a(7)) xor 
                 (b(4) and a(2)) xor (b(4) and a(6)) xor (b(4) and a(7)) xor (b(5) and a(1)) xor (b(5) and a(5)) xor 
                 (b(5) and a(6)) xor (b(5) and a(7)) xor (b(6) and a(0)) xor (b(6) and a(4)) xor (b(6) and a(5)) xor 
                 (b(6) and a(6)) xor (b(7) and a(3)) xor (b(7) and a(4)) xor (b(7) and a(5));
    result(7) := (b(0) and a(7)) xor (b(1) and a(6)) xor (b(2) and a(5)) xor (b(3) and a(4)) xor (b(4) and a(3)) xor 
                 (b(4) and a(7)) xor (b(5) and a(2)) xor (b(5) and a(6)) xor (b(5) and a(7)) xor (b(6) and a(1)) xor 
                 (b(6) and a(5)) xor (b(6) and a(6)) xor (b(6) and a(7)) xor (b(7) and a(0)) xor (b(7) and a(4)) xor 
                 (b(7) and a(5)) xor (b(7) and a(6));
  return result;
end f_rscalcul;
  -- gin0.....gin15 (8 bits each ) = 
 
  -- Generator polynomial co-effcients. 
 
  -- The generator polynomial is form X^16 + gin15 X^15 + gin14 X^14 + ...... gin1 X + gin0.
 
  -- Each gi (i=0, 1, ...15) is an element of GF(2^8);
 
  signal gin       : Tab_std_vector8(15 downto 0); -- coefficients du polynome générateur
 
  signal fback     : std_logic_vector(7 downto 0); -- initialisation ?
 
  signal val_fec   : Tab_std_vector8(15 downto 0); -- z dans le code initial
 
begin
  gin(0)  <= std_logic_vector(to_unsigned( 59,8));  -- 136   59   x"21"  assign GPol1  = 59; 
 
  gin(1)  <= std_logic_vector(to_unsigned( 36,8));  -- 240   13   x"AB"  assign GPol2  = 13; 
 
  gin(2)  <= std_logic_vector(to_unsigned( 50,8));  -- 208  104   x"21"  assign GPol3  = 104;
 
  gin(3)  <= std_logic_vector(to_unsigned( 98,8));  -- 195  189   x"8E"  assign GPol4  = 189;
 
  gin(4)  <= std_logic_vector(to_unsigned(229,8));  -- 181   68   x"93"  assign GPol5  = 68; 
 
  gin(5)  <= std_logic_vector(to_unsigned( 41,8));  -- 158  209   x"AB"  assign GPol6  = 209;
 
  gin(6)  <= std_logic_vector(to_unsigned( 65,8));  -- 201   30   x"8E"  assign GPol7  = 30; 
 
  gin(7)  <= std_logic_vector(to_unsigned(163,8));  -- 100    8   x"CD"  assign GPol8  = 8;  
 
  gin(8)  <= std_logic_vector(to_unsigned(  8,8));  --  11  163   x"FA"  assign GPol9  = 163;
 
  gin(9)  <= std_logic_vector(to_unsigned( 30,8));  --  83   65   x"EE"  assign GPol10 = 65; 
 
  gin(10) <= std_logic_vector(to_unsigned(209,8));  -- 167   41   x"FF"  assign GPol11 = 41; 
 
  gin(11) <= std_logic_vector(to_unsigned( 68,8));  -- 107  229   x"0C"  assign GPol12 = 229;
 
  gin(12) <= std_logic_vector(to_unsigned(189,8));  -- 113   98   x"AB"  assign GPol13 = 98; 
 
  gin(13) <= std_logic_vector(to_unsigned(104,8));  -- 110   50   x"26"  assign GPol14 = 50; 
 
  gin(14) <= std_logic_vector(to_unsigned( 13,8));  -- 106   36   x"35"  assign GPol15 = 36; 
 
  gin(15) <= std_logic_vector(to_unsigned( 59,8));  -- 121   59   x"89"  assign GPol16 = 59; 
 
  
  fback <= (val_fec(15) xor din) when (ce_fec='1') else (others => '0');
  cal_rs_proc: process(xgsr,clk)
  begin
    if (xgsr ='1') then
        for i in 0 to 15 loop
          val_fec(i) <= (others =>'0');
        end loop;
        dout      <= (others =>'0'); 
    elsif rising_edge(clk) then
        if (ce='1') then
    
            -- val_fec = x^(n-k).u(x).mod[g(x)]
 
            val_fec(0) <= f_gfmult(fback, gin(0));   
              for i in 1 to 15 loop
                val_fec(i) <= val_fec(i-1) xor f_gfmult(fback, gin(i));
              end loop;
            -- mux output control : k information symbol and n-k parity
 
            if (ce_fec='1') then
                dout <= din;          
            else          
                dout <= val_fec(15);
            end if;
            
       end if;
    end if;
  end process cal_rs_proc;
end A;
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